FIG. 1 is a block diagram of a prior art phase shift key receiver employing digital processing. The receiver is responsive to a noise ladened suppressed carrier quadrature phase shift key (QPSK) modulated electromagnetic wave incident on antenna 10. The wave incident on antenna 10 is transduced into an electrical signal that is amplified by RF and IF stages 12. The wave has a precisely controlled carrier frequency determined at an electromagnetic wave QPSK transmitter and includes symbols having a predetermined rate, i.e., frequency, e.g., 20 mHz.
The output signal of stages 12 is applied in parallel to mixers 14 and 16, also respectively responsive to mutually orthogonal oscillations derived by .+-.45.degree. phase shifters 18 and 20. Phase shifters 18 and 20 are in turn responsive to voltage controlled variable frequency local oscillator 22, having an output frequency approximately equal to the suppressed carrier frequency derived from stages 12. The resulting outputs of mixers 18 and 20 are respectively applied to matched (to the transmitter waveform) low-pass filters 24 and 26 which derive variable analog baseband signals representing symbols to be processed into intelligence representing output signals. The baseband output signals of filters 24 and 26 are typically referred to as I and Q channel signals.
The I and Q channel signals derived by filters 24 and 26 are respectively applied via variable gain amplifiers 23 and 25 to analog-to-digital converters 28 and 30, operated to sample the baseband I and Q signal amplitudes at a variable frequency, typically approximately twice the symbol frequency. The gains of amplifiers 23 and 25 are controlled so that the maximum amplitude of the analog signals supplied to converters 28 and 30 equals the optimal range which the converters can handle. In normal operation, converters 28 and 30 sample the I and Q channel signals supplied to them twice per symbol, approximately in the center and between adjacent symbols. Converters 28 and 30 derive multibit digital output signals representing the magnitude and polarity of each sample applied to the converters. Converters 28 and 30, included on separate integrated circuit chips, are relatively expensive because they must sample the baseband I and Q channel analog signals at a frequency of approximately 40 mHz.
The I and Q representing digital signals derived by converters 28 and 30 are applied in parallel to carrier tracker 32, symbol tracker 34 and amplitude tracker 36, all of which are digital processing circuits included on a single custom integrated circuit chip. Carrier tracker 32 derives a digital signal having a value representing the polarity and magnitude of the frequency and phase differences between the output of oscillator 22 and the suppressed carrier output of stages 12. Symbol tracker 34 derives a digital signal having a value representing the polarity and magnitude of an error in the sampling times of converters 28 and 30 relative to idealized positions for these sampling times. Amplitude tracker 36 responds to the I and Q outputs of converters 28 and 30 and a reference value for the optimal amplitude at which the converters should operate to derive a control signal for variable gain amplifiers 23 and 25. The I and Q output signals of converters 28 and 30 are also applied to output processing circuit 37. Typically, the digital signals have eight to ten bits, particularly to provide necessary resolution for control of amplifiers 23 and 25.
The digital signals derived by trackers 32, 34 and 36 are respectively applied to digital to analog converters 38, 40 and 42, having analog output signals respectively applied to low-pass filters 44, 46 and 48. The output signal of filter 44 controls the frequency and phase of oscillator 22 so they are ideally equal to the frequency and phase of the suppressed carrier frequency derived from stages 12. The output of filter 46 is supplied to voltage controlled, variable frequency oscillator 50, having an output controlling the phase of clock pulses derived by clock source 51. The clock pulses derived by source 51 are applied in parallel to clock inputs of analog-to-digital converters 28 and 30, to control when the converters take samples of the analog inputs supplied to them. The clock pulses supplied to the clock input of converters 28 and 30 have a frequency approximately equal to twice the frequency of the symbols applied to the converters. The output of low-pass filter 48 is supplied in parallel to gain control inputs of variable gain amplifiers 28 and 25.
While the apparatus of FIG. 1 performs satisfactorily, it is excessively expensive for consumer applications, involving manufacture of perhaps millions of units, and wherein cost savings of even a few cents per unit can be critical. A primary expense associated with the apparatus illustrated in FIG. 1 is the requirement for two samples of each symbol to be taken by analog to digital converters 28 and 30. The cost of the analog-to-digital converters and the digital processing circuits they drive increases appreciably as the frequency of operation thereof increases. The need for three digital-to-analog converters and the low-pass filters associated therewith also adds appreciably to the cost of the apparatus illustrated in FIG. 1. Converter 46, in particular, must derive an output signal having at least eight bits for proper control of variable gain amplifiers 23 and 25.
It is, accordingly, an object of the present invention to provide a new and improved, relatively inexpensive receiver and demodulator for digitally processing signals modulated by symbols.
Another object of the invention is to provide a new and improved receiver and demodulator for digitally processing signals modulated by symbols wherein only a single sample of an analog signal is taken of each symbol.
An additional object of the invention is to provide a new and improved receiver and demodulator for digitally processing signals modulated by symbols including only digital processing for control of carrier and symbol tracking.
A further object of the invention is to provide a new and improved receiver for digitally processing signals modulated by symbols, wherein the receiver employs a nominally fixed frequency local source digital circuitry responsive to an analog-to-digital converter output corrects for frequency and phase errors between the actual frequency derived by the source and a carrier for the modulated signal.
An additional object of the invention is to provide a new and improved receiver and demodulator for digitally processing signals modulated by symbols, wherein the receiver employs digital processing circuitry and a relatively inexpensive digital-to-analog converter is employed for controlling the amplitude of baseband analog signals applied to analog-to-digital converter circuitry.